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b6b7d72717
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304
riscv_cpu_fp_template.h
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304
riscv_cpu_fp_template.h
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/*
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* RISCV emulator
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*
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* Copyright (c) 2016 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#if F_SIZE == 32
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#define OPID 0
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#define F_HIGH F32_HIGH
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#elif F_SIZE == 64
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#define OPID 1
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#define F_HIGH F64_HIGH
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#elif F_SIZE == 128
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#define OPID 3
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#define F_HIGH 0
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#else
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#error unsupported F_SIZE
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#endif
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#define FSIGN_MASK glue(FSIGN_MASK, F_SIZE)
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case (0x00 << 2) | OPID:
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rm = get_insn_rm(s, rm);
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if (rm < 0)
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goto illegal_insn;
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s->fp_reg[rd] = glue(add_sf, F_SIZE)(s->fp_reg[rs1],
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s->fp_reg[rs2],
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rm, &s->fflags) | F_HIGH;
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s->fs = 3;
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break;
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case (0x01 << 2) | OPID:
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rm = get_insn_rm(s, rm);
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if (rm < 0)
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goto illegal_insn;
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s->fp_reg[rd] = glue(sub_sf, F_SIZE)(s->fp_reg[rs1],
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s->fp_reg[rs2],
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rm, &s->fflags) | F_HIGH;
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s->fs = 3;
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break;
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case (0x02 << 2) | OPID:
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rm = get_insn_rm(s, rm);
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if (rm < 0)
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goto illegal_insn;
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s->fp_reg[rd] = glue(mul_sf, F_SIZE)(s->fp_reg[rs1],
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s->fp_reg[rs2],
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rm, &s->fflags) | F_HIGH;
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s->fs = 3;
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break;
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case (0x03 << 2) | OPID:
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rm = get_insn_rm(s, rm);
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if (rm < 0)
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goto illegal_insn;
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s->fp_reg[rd] = glue(div_sf, F_SIZE)(s->fp_reg[rs1],
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s->fp_reg[rs2],
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rm, &s->fflags) | F_HIGH;
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s->fs = 3;
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break;
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case (0x0b << 2) | OPID:
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rm = get_insn_rm(s, rm);
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if (rm < 0 || rs2 != 0)
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goto illegal_insn;
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s->fp_reg[rd] = glue(sqrt_sf, F_SIZE)(s->fp_reg[rs1],
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rm, &s->fflags) | F_HIGH;
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s->fs = 3;
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break;
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case (0x04 << 2) | OPID:
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switch(rm) {
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case 0: /* fsgnj */
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s->fp_reg[rd] = (s->fp_reg[rs1] & ~FSIGN_MASK) |
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(s->fp_reg[rs2] & FSIGN_MASK);
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break;
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case 1: /* fsgnjn */
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s->fp_reg[rd] = (s->fp_reg[rs1] & ~FSIGN_MASK) |
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((s->fp_reg[rs2] & FSIGN_MASK) ^ FSIGN_MASK);
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break;
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case 2: /* fsgnjx */
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s->fp_reg[rd] = s->fp_reg[rs1] ^
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(s->fp_reg[rs2] & FSIGN_MASK);
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break;
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default:
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goto illegal_insn;
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}
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s->fs = 3;
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break;
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case (0x05 << 2) | OPID:
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switch(rm) {
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case 0: /* fmin */
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s->fp_reg[rd] = glue(min_sf, F_SIZE)(s->fp_reg[rs1],
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s->fp_reg[rs2],
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&s->fflags,
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FMINMAX_IEEE754_201X) | F_HIGH;
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break;
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case 1: /* fmax */
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s->fp_reg[rd] = glue(max_sf, F_SIZE)(s->fp_reg[rs1],
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s->fp_reg[rs2],
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&s->fflags,
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FMINMAX_IEEE754_201X) | F_HIGH;
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break;
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default:
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goto illegal_insn;
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}
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s->fs = 3;
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break;
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case (0x18 << 2) | OPID:
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rm = get_insn_rm(s, rm);
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if (rm < 0)
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goto illegal_insn;
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switch(rs2) {
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case 0: /* fcvt.w.[sdq] */
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val = (int32_t)glue(glue(cvt_sf, F_SIZE), _i32)(s->fp_reg[rs1], rm,
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&s->fflags);
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break;
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case 1: /* fcvt.wu.[sdq] */
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val = (int32_t)glue(glue(cvt_sf, F_SIZE), _u32)(s->fp_reg[rs1], rm,
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&s->fflags);
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break;
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#if XLEN >= 64
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case 2: /* fcvt.l.[sdq] */
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val = (int64_t)glue(glue(cvt_sf, F_SIZE), _i64)(s->fp_reg[rs1], rm,
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&s->fflags);
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break;
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case 3: /* fcvt.lu.[sdq] */
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val = (int64_t)glue(glue(cvt_sf, F_SIZE), _u64)(s->fp_reg[rs1], rm,
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&s->fflags);
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break;
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#endif
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#if XLEN >= 128
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/* XXX: the index is not defined in the spec */
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case 4: /* fcvt.t.[sdq] */
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val = glue(glue(cvt_sf, F_SIZE), _i128)(s->fp_reg[rs1], rm,
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&s->fflags);
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break;
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case 5: /* fcvt.tu.[sdq] */
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val = glue(glue(cvt_sf, F_SIZE), _u128)(s->fp_reg[rs1], rm,
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&s->fflags);
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break;
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#endif
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default:
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goto illegal_insn;
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}
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if (rd != 0)
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s->reg[rd] = val;
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break;
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case (0x14 << 2) | OPID:
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switch(rm) {
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case 0: /* fle */
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val = glue(le_sf, F_SIZE)(s->fp_reg[rs1], s->fp_reg[rs2],
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&s->fflags);
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break;
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case 1: /* flt */
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val = glue(lt_sf, F_SIZE)(s->fp_reg[rs1], s->fp_reg[rs2],
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&s->fflags);
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break;
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case 2: /* feq */
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val = glue(eq_quiet_sf, F_SIZE)(s->fp_reg[rs1], s->fp_reg[rs2],
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&s->fflags);
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break;
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default:
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goto illegal_insn;
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}
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if (rd != 0)
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s->reg[rd] = val;
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break;
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case (0x1a << 2) | OPID:
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rm = get_insn_rm(s, rm);
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if (rm < 0)
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goto illegal_insn;
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switch(rs2) {
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case 0: /* fcvt.[sdq].w */
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s->fp_reg[rd] = glue(cvt_i32_sf, F_SIZE)(s->reg[rs1], rm,
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&s->fflags) | F_HIGH;
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break;
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case 1: /* fcvt.[sdq].wu */
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s->fp_reg[rd] = glue(cvt_u32_sf, F_SIZE)(s->reg[rs1], rm,
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&s->fflags) | F_HIGH;
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break;
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#if XLEN >= 64
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case 2: /* fcvt.[sdq].l */
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s->fp_reg[rd] = glue(cvt_i64_sf, F_SIZE)(s->reg[rs1], rm,
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&s->fflags) | F_HIGH;
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break;
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case 3: /* fcvt.[sdq].lu */
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s->fp_reg[rd] = glue(cvt_u64_sf, F_SIZE)(s->reg[rs1], rm,
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&s->fflags) | F_HIGH;
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break;
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#endif
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#if XLEN >= 128
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/* XXX: the index is not defined in the spec */
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case 4: /* fcvt.[sdq].t */
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s->fp_reg[rd] = glue(cvt_i128_sf, F_SIZE)(s->reg[rs1], rm,
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&s->fflags) | F_HIGH;
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break;
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case 5: /* fcvt.[sdq].tu */
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s->fp_reg[rd] = glue(cvt_u128_sf, F_SIZE)(s->reg[rs1], rm,
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&s->fflags) | F_HIGH;
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break;
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#endif
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default:
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goto illegal_insn;
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}
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s->fs = 3;
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break;
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case (0x08 << 2) | OPID:
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rm = get_insn_rm(s, rm);
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if (rm < 0)
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goto illegal_insn;
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switch(rs2) {
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#if F_SIZE == 32 && FLEN >= 64
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case 1: /* cvt.s.d */
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s->fp_reg[rd] = cvt_sf64_sf32(s->fp_reg[rs1], rm, &s->fflags) | F32_HIGH;
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break;
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#if FLEN >= 128
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case 3: /* cvt.s.q */
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s->fp_reg[rd] = cvt_sf128_sf32(s->fp_reg[rs1], rm, &s->fflags) | F32_HIGH;
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break;
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#endif
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#endif /* F_SIZE == 32 */
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#if F_SIZE == 64
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case 0: /* cvt.d.s */
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s->fp_reg[rd] = cvt_sf32_sf64(s->fp_reg[rs1], &s->fflags) | F64_HIGH;
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break;
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#if FLEN >= 128
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case 1: /* cvt.d.q */
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s->fp_reg[rd] = cvt_sf128_sf64(s->fp_reg[rs1], rm, &s->fflags) | F64_HIGH;
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break;
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#endif
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#endif /* F_SIZE == 64 */
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#if F_SIZE == 128
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case 0: /* cvt.q.s */
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s->fp_reg[rd] = cvt_sf32_sf128(s->fp_reg[rs1], &s->fflags);
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break;
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case 1: /* cvt.q.d */
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s->fp_reg[rd] = cvt_sf64_sf128(s->fp_reg[rs1], &s->fflags);
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break;
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#endif /* F_SIZE == 128 */
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default:
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goto illegal_insn;
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}
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s->fs = 3;
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break;
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case (0x1c << 2) | OPID:
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if (rs2 != 0)
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goto illegal_insn;
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switch(rm) {
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#if F_SIZE <= XLEN
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case 0: /* fmv.x.s */
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#if F_SIZE == 32
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val = (int32_t)s->fp_reg[rs1];
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#elif F_SIZE == 64
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val = (int64_t)s->fp_reg[rs1];
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#else
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val = (int128_t)s->fp_reg[rs1];
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#endif
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break;
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#endif /* F_SIZE <= XLEN */
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case 1: /* fclass */
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val = glue(fclass_sf, F_SIZE)(s->fp_reg[rs1]);
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break;
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default:
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goto illegal_insn;
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}
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if (rd != 0)
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s->reg[rd] = val;
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break;
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#if F_SIZE <= XLEN
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case (0x1e << 2) | OPID: /* fmv.s.x */
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if (rs2 != 0 || rm != 0)
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goto illegal_insn;
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#if F_SIZE == 32
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s->fp_reg[rd] = (int32_t)s->reg[rs1];
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#elif F_SIZE == 64
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s->fp_reg[rd] = (int64_t)s->reg[rs1];
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#else
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s->fp_reg[rd] = (int128_t)s->reg[rs1];
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#endif
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s->fs = 3;
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break;
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#endif /* F_SIZE <= XLEN */
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#undef F_SIZE
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#undef F_HIGH
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#undef OPID
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#undef FSIGN_MASK
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